1. Field of the Invention
The present invention relates to an active matrix type of a liquid crystal display device using a thin film transistor and a method of manufacturing the same.
2. Description of the Related Art
In recent years, a display device having a larger screen and higher fineness is requested in order to miniaturize and lighten a personal computer and a word processor. For this purpose, an active matrix type of a liquid crystal display device is generally used. In this display device, a semiconductor thin film transistor is formed on a transparent insulation substrate as an actively switching element.
For example, a liquid crystal display device is used which has a configuration as shown in FIG. 1. FIG. 1 is a plan view showing a liquid crystal display device. A color filter substrate CB is placed in an upper portion of a TFT substrate K shown in FIG. 1 although it is omitted here. The circuit structure of the liquid crystal display device will be described below with reference to FIG. 2. FIG. 2 is an equivalent circuit to the liquid crystal display device of FIG. 1.
In FIG. 2, semiconductor thin film transistors TR11 to TRnm are respectively formed in the vicinities of respective intersections of respective data lines D1 to Dm and data selection lines S1 to Sn in order to drive respective pixels in the liquid crystal display device. The data lines D1 to Dm are connected to respective drain terminals of the thin film transistors TR11 to TR1m, . . . , and TRn1 to TRnm. The pixels CG are connected to respective sources of the thin film transistors TR11 to TRnm. Display data signals D1 to Dm are supplied to columns of the respective pixels CG from an external drive IC (Integrated Circuit) (not shown) to the data lines D1 to Dm through respective terminals TD1 to TDm. Also, selection signals are supplied from an external drive IC (not shown) to the data selection lines S1 to Sn through respective terminals TG1 to TGn. Thus, one of the thin film transistors is selected for each of the columns of the pixels CG. At this time, the liquid crystal display device sequentially enters the display data signals to the respective data lines D1 to Dm at predetermined timings. Also, the data selection signals are sequentially supplied to the data selection lines S1 to Sn in response to those timings to turn on the thin film transistors TR11 to TR1m, . . . , and TRn1 to TRnm.
Thus, predetermined charges corresponding to the display data signals are accumulated in capacitors CG as the pixels from the respective data lines D1 to Dm through the respective thin film transistors TR11 to TRnm. The pixel capacitor CG is formed of a pixel electrode, a counter electrode and a liquid crystal layer between them. The counter electrode is formed in the color filter substrate CB (not shown) and is set to a predetermined potential Va. Here, the pixel electrode implies a pattern of a transparent electrode 12 formed in an area of the pixel CG.
However, the charge accumulated in the pixel capacitor CG is gradually naturally discharged and reduced. Thus, a potential difference between the pixel electrode and the counter electrode is dropped so that an orientation of each of molecules of the liquid crystal can not be kept at a predetermined position until a next accumulation of charges is carried out. That is, this results in the occurrence of variation of a display intensity in which the display becomes extremely dark or bright. For this reason, respective accumulation capacitor elements C11 to Cnm are provided in parallel with the pixel capacitors CG in order to compensate the discharged charges. Also, a predetermined voltage is applied through respective terminals TG2 to TGn and the electrodes TC from the drive ICs (not shown) to the other terminal opposite to a terminal connected to the pixel capacitor CG in each of the accumulation capacitor elements C11 to Cnm.
Next, a method for manufacturing the liquid crystal display device will be described below with reference to FIGS. 3A to 3E. This method is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-48664). FIGS. 3A to 3E show the cross sectional views of the liquid crystal display device taken on a line A—A in FIG. 1.
In FIG. 3A, a chrome layer MT1 is deposited on a surface of a transparent glass substrate 1 by use of a technique such as a sputtering or CVD (Chemical Vapor Deposition) method. Subsequently, a resist pattern (not shown) is formed in an area for patterns such as a gate electrode on the surface of the conductive layer MT1 are formed by use of a typical photolithography technique. Then, the conductive layer MT1 is etched by use of the resist pattern (not shown) as a mask. Thus, a terminal pattern 2, a gate electrode pattern 3 and a gate bus line pattern 4 are formed. Here, the gate electrode pattern 3 implies a pattern area formed to protrude from the gate bus line pattern 4 and acts as the gate electrode of the thin film transistor (each of the thin film transistors TR11 to TRnm), as shown in FIG. 1.
Next, in FIG. 3B, a gate insulating film 5 is formed as a layer of silicon nitride film on the transparent glass substrate 1. Then, an i-type (intrinsic type) a-Si (amorphous silicon) layer 6 and an n+ type a-Si layer 7 for the thin film transistor (each of the thin film transistors TR11 to TRnm in FIG. 1) are laminated above the surface of the gate insulating film 5. Next, a resist pattern (not shown) is formed in the area for the thin film transistor on the surface of the n+ type a-Si layer 7 by use of the typical photolithography technique. Then, the a-Si layer 6 and the n+ type a-Si layer 7 are etched by use of the resist pattern (not shown) as a mask. Thus, the a-Si layer 6 and the n+ type a-Si layer 7 are formed for the pattern of the thin film transistor.
Next, in FIG. 3C, a chrome layer (conductive layer) MT2 is deposited on the surface of the n+ type a-Si layer 7 and the surface of the gate insulating film 5 by use of a sputtering method or a CVD method. The chrome layer MT2 is a drain electrode and source electrode of the thin film transistor and is the second electrode 10 as another terminal of an accumulation capacitor element (each of the accumulation capacitor elements C11 to Cnm).
Next, a resist patterns (not shown) is formed in the areas for the second electrode 10 of the accumulation capacitor element and for the drain and source electrodes of the thin film transistor on the surface of the conductive layer MT2 by use of the typical photolithography technique. Then, the conductive layer MT2 is etched by use of the resist pattern (not shown) as a mask. Thus, a drain electrode 8 and a source electrode 9 are formed in the positions of the patterns of the drain and the source in the thin film transistor, respectively. Also, the second electrode 10 is formed in the position of the terminal pattern of the accumulation capacitor element. After that, the drain electrode 8 and the source electrode 9 are used as a mask to remove the n+ type a-Si layer 7 remaining on the channel area of each of the thin film transistors TR11 to TRnm.
Next, as shown in FIG. 3D, a protective insulating film 11 is deposited on the surfaces of the drain electrode 8, source electrode 9 and second electrode 10 and the surface of the gate insulating film 5 by use of a sputtering method and a CVD method. Subsequently, a resist pattern (not shown) is formed for contact holes CT in the protective insulating film 11 by use of the typical photolithography technique. Then, the resist pattern (not shown) is used as a mask to etch the protective insulating film 11. Thus, openings for the contact hole CT are formed at the predetermined positions of the protective insulating film 11. At this time, the gate insulating film 5 is etched in the terminal 2 in addition to the protective insulating film 11. Hence, the surface of the terminal 2 is exposed.
Next, as shown in FIG. 3E, a transparent conductive layer such as an ITO (Indium Tin Oxide) layer 12 is formed on the surface of the protective insulating film 11, the surface of the terminal pattern 2 exposed through the contact hole CT, the surface of the pattern of the source electrode 9 exposed through the contact hole CT, and the surface of the gate bus line pattern 4 exposed through the contact hole CT by use of a sputtering method. A resist pattern (not shown) is formed for predetermined areas of the conductive layer 12 serving as a wiring patterns and a pixel electrode by use of the typical photolithography technique. The conductive layer 12 is etched by use of the resist pattern (not shown) as a mask. Thus, the pixel electrode (pattern of the conductive layer 12 on the pixel CG) is formed of the conductive layer 12, and the pixel electrode and the second electrode 10 are connected to each other through the contact hole CT. The TFT (Thin Film Transistor) array substrate is completed by the above-mentioned processes.
In this way, each of the accumulation capacitor elements C11 to Cnm is formed of the gate bus line pattern 4 (constituted of the metal layer MT1), the gate insulating film 5 and the second electrode 10. If there is no accumulation capacitor element, the pixel capacitor must be formed to have larger capacitance. However, since the protective insulating film 11 is added, the capacitance value can not be made larger.
Next, in FIG. 4 (the portion of the terminal pattern 2 is omitted), an orientation film 13 made of material such as polyimide resin, is coated on the surface of the protective insulating film 11 and the surface of the wiring pattern of the conductive layer 12. Then, the surface of the orientation film 13 is rubbed with a roller (a rubbing process), such that the molecules of the liquid crystal are oriented on the surface of the orientation film.
Similarly, the color filter substrate CB is produced to be placed on the glass substrate 1. Here, the color filter substrate CB is formed on the surface of a glass substrate 20, and a black matrix layer 21 is made of metal material such as CR. Then, a coloration film 22 is laminated on the surface on the black matrix layer 21. Next, a counter electrode layer 23 having a transparent conductive layer such as an ITO layer is laminated on the surface of the coloration film 22. Then, an orientation film 24 made of material such as polyimide resin, is coated on the surface of the counter electrode 23. Then, the surface of the orientation film 24 is rubbed with a roller (the rubbing process) so that the molecules of the liquid crystal are oriented on the surface of the orientation film 24.
The TFT substrate K and the color filter substrate CB are fit to each other through a spacer with a predetermined distance so that the orientation films 13, 24 face each other. Next, liquid crystal 14 is injected into the gap between the TFT substrate K and the color filter substrate CB and the gap between the TFT substrate K and the color filter substrate CB is sealed. Next, a polarization plate 15 and a polarization plate 25 are fit on a rear surface of the glass substrate 1 and a rear surface of the glass substrate 20, respectively. Then, a drive circuit and a body are added to complete the liquid crystal display device.
However, in the above-mentioned liquid crystal display device, there is a case where a short-circuited defect is induced between the pixel electrode and a first electrode of the accumulation capacitor element (the gate bus line pattern 4 in this case) in a process for manufacturing the element. The mechanism of the occurrence of the short-circuited defect in the manufacturing process will be described below with reference to FIGS. 5A to 5F. FIGS. 5A to 5F show cross sectional views of the liquid crystal display device taken on a line B—B in FIG. 1.
In the process shown in FIG. 3A, it is supposed that when the conductive layer MT2 is deposited on the surface of the gate insulating film 5, a film formation defect FA1 is induced in the conductive layer MT2 on the upper portion of the gate bus line pattern 4 because of dust on the film surface, as shown in FIG. 5A. Then, a photo-resist R1 for the second electrode 10 is formed by use of the photolithography technique, as shown in FIG. 5B. Thus, the conductive layer MT2 is etched with the photo-resist R1 as a mask. Hence, when the resist R1 is removed, the shape shown in FIG. 5C is provided. Subsequently, as shown in FIG. 5D, the protective insulating film 11 is deposited on the surface of the second electrode 10 and the surface of the gate insulating film 5. Next, a photo-resist R2 is coated on the surface of the protective insulating film 11. A pattern for a contact hole CT is formed to the photo-resist R2 by use of the photolithography technique. Thus, the protective insulating film 11 is etched by use of the photo-resist R2 as a mask. Hence, when the resist R2 is removed, the shape shown in FIG. 5E is formed.
However, at this time, thicknesses to be etched are different between the portion of the terminal pattern 2 and the accumulation capacitor element, as can be seen from FIG. 3D. That is, if only the protective insulating film 11 is etched in the portion of the second electrode 10, the surface of the second electrode 10 is exposed. However, it is necessary to etch both of the protective insulating film 11 and the gate insulating film 5 in the portion of the terminal pattern 2. For the reason, an etching time period in which the protective insulating film 11 and the gate insulating film 5 can be sufficiently removed is set. As a result, if there is no film formation defect FA1 in the second electrode 10, the second electrode 10 acts as a stopper so that the etching does not proceed. However, if there is the film formation defect FA1, the etching proceeds up to the gate bus line 4. Thus, a film formation defect FA2 is induced in the gate insulating film 5 as shown in FIG. 5E.
In FIG. 5F, when the pattern of the conductive layer 12 is formed, the second electrode 10 and the gate bus line 4 are short-circuited through the film formation defect FA2. As a result, if the second electrode 10 and the gate bus line 4 are short-circuited in the accumulation capacitor element C11 in FIG. 1, the thin film transistor TR11 is turned on. Even if the charge is injected into the pixel CG, a voltage of the pixel CG is always equal to that of the gate bus line 4. This is because the path of charge is formed from the second electrode 10 of the accumulation capacitor element C11 to the gate bus line 4. As a result, the pixel CG having the short-circuited defect is recognized as a point defect, which drops a display device quality.
In order to prevent the short-circuited defect from being induced, it is enough to etch the gate insulating film 5 after masking the portion other than the terminal pattern 2, after etching only the protective insulating film 11. However, the not only a mask increase by 1, but also the second electrode 10 exposed in the contact hole CT is contaminated. Thus, a contact resistance in the contact hole CT is increased so that the charge can not be sufficiently charged to the accumulation capacitor element. Hence, the etching process is carried out by use of the same mask for the protective insulating film 11 and the gate insulating film 5.
If there is a defect in the photo-resist R1 serving as a mask of the etching even though any defect is not induced when the conductive layer MT2 is formed, the short-circuited defect is induced between the second electrode 10 and the gate bus line 4, similarly to the above-mentioned case. This short-circuited defect will be described below with reference to FIGS. 6A to 6C. FIGS. 6A to 6C show cross section views of the liquid crystal display device taken on the line B—B in FIG. 1.
For example, in FIG. 3A, it is supposed that the conductive layer MT2 is deposited on the surface of the gate insulating film 5 to thereby provide the structure shown in FIG. 6A. Then, a photo-resist R1 for a second electrode 10 is formed by use of the photolithography technique as shown in FIG. 6B. At this time, it is supposed that a resist defect FR1 is induced in which a babble is mixed in the photo-resist R1. As a result, the conductive layer MT2 is etched by use of the photo-resist R1 as a mask. Thus, when the photo-resist R1 is removed, the shape shown in FIG. 6C is formed. At this time, the conductive layer MT2 is etched by use of the photo-resist R1 having the resist defect FR1 as a mask. Thus, the film defect FA3 is induced in the conductive layer MT2, similarly to the case of FIG. 5C. The occurrence of the short-circuited defect between the second electrode 10 and the gate bus line pattern 4 is similar to the description in FIGS. 5D to 5F except that the film formation defect FA1 is replaced by the film defect FA3. Accordingly, the description thereof is omitted.
In order to avoid the above-mentioned problems, the countermeasure in which the position of the contact hole CT in the second electrode 10 is displaced from the first electrode of the accumulation capacitor element is considered, as shown in Japanese Laid Open Patent Application (JP-A-Heisei, 9-15644). The structure of the above-mentioned liquid crystal display device will be described below with reference to FIG. 7. FIG. 7 is a partial expanded plan view of a portion of one pixel in a liquid crystal display device as another conventional example. In FIG. 7, an accumulation capacitor element (each of the accumulation capacitor elements C11 to Cnm) is formed between a second electrode 10 (an auxiliary electrode) and a common potential line pattern 40 separately from the gate bus line pattern 4 of the liquid crystal display device in the above conventional example. The common potential line-pattern 40 is formed on the same conductive layer as the gate bus line pattern 4 in the conventional example. Accordingly, the process is same. In the way, there are two kinds in the structure of the accumulation capacitor element. That is, one is the accumulation capacitor element formed of the gate bus line pattern 4 and the second electrode 10 in the liquid crystal display device as shown in FIG. 1. The other is the accumulation capacitor element formed of the common potential line pattern 40 and the second electrode 10.
The structure of the liquid crystal display device shown in FIG. 7 will be described below. Here, the structure of the thin film transistor TR is similar to those of the thin film transistors TR11 to Trnm shown in FIG. 1. Thus, the description thereof is omitted. Accordingly, the structure of the accumulation capacitor elements C11 to Cnm will be described below with reference to FIG. 8 showing a cross sectional view of the liquid crystal display device taken on along the line C—C in FIG. 7.
In FIG. 8, a common potential line pattern 40 is formed on a surface of an insulation substrate 1, and a gate insulating film 5 is formed on the surface of the insulation substrate 1 and the surface of the common potential line pattern 40. Then, an a-Si layer 6, an n+ type a-Si layer 7 and a second electrode 10 are formed as a stack structure, in order to form an accumulation capacitor element C11 at a gate bus line pattern 4. That is, the a-Si layer 6, the n+ type a-Si layer 7 and the conductive layer MT2 are sequentially laminated. Then, these layers are formed through once etching process by use of the photo-resist as the mask for forming a counter electrode. Subsequently, a contact hole CT is formed, and a wiring pattern of a conductive layer 12 is formed by the above-mentioned processes. If there is a defect in a photo-resist serving as a mask for forming the counter electrode, a film defect is induced which penetrates the respective layers of the a-Si layer 6, the n+ type a-Si layer 7 and the second electrode 10 for the counter electrode. However, the short-circuited defect is never induced between the second electrode 10 of the conductive layer 12 and the first electrode of the accumulation capacitor element, even if a gate insulating film 5 over-etched when the contact hole CT is formed in the terminal pattern 2 in FIG. 1. This is because the first electrode (the common potential line pattern 40 in the case) of the accumulation capacitor element is displaced from the contact hole CT. However, an aperture rate of a pixel CG is reduced on the basis of an area of a portion in which the second electrode 10 is displaced into an outer portion of the first electrode of the accumulation capacitor element.
This reason is as follows. That is, in the case of FIG. 1, the contact hole CT is located above the gate bus line pattern 4, and the gate bus line pattern 4 is opaque. Therefore, even if the contact hole CT is formed, the aperture rate is never reduced. However, in the case of FIG. 7, the contact hole CT is displaced so as not to be located at the upper portion of the first electrode of the accumulation capacitor element. Thus, the area of the opaque portion is increased, and the aperture rate is reduced. As a result, the display intensity of the pixel is reduced. Hence, it is desirable that the contact between the second electrode 10 of the accumulation capacitor element and the pixel electrode is formed at the upper portion of the first electrode of the accumulation capacitor element so as not to reduce the aperture rate.
Also, in the accumulation capacitor elements C11 of FIG. 8 (the accumulation capacitor elements C12 to Cnm), the a-Si layer 6 and the n+ type a-Si layer 7 exist in the entire lower portion of the second electrode 10. Thus, a considerable portion acts as an MIS (Metal-Insulator-Semiconductor) capacitor having an MIS structure. Hence, a capacitance value is smaller as compared with the area.
In conjunction with the above description, an active matrix type liquid crystal display device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-339885). In this reference, a metal layer CstDM is disposed in a protection film PAS and a gate insulating film put between a transparent pixel electrode ITO and a previous stage scanning signal line layer GM. The metal layer CstDM is formed of the same material as an image signal line. Thus, the effective distance between capacitor electrodes can be reduced and the capacitance can be made large without widening the area.
Also, an active matrix type liquid crystal display device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-38439). In this reference, a pixel electrode 111 is formed on surface protection film deposited on a TFT 100. A capacitor electrode 112 is formed on the same layer as the TFT 100 to be electrically connected to a pixel electrode 111 through a via-hole 114. An accumulation capacitor is composed of a capacitor electrode 103 formed on a glass substrate 101 and the capacitor electrode 112 formed via the gate insulating film 104.